Thin silicon layers which have properties different from those of single crystal silicon substrates are commonly used for the processing of many types of semiconductor devices. Such layers are typically between 0.1 μm and 100 μm thick but can be even thicker than 100 μm or thinner than 0.1 μm. The layers can be single crystalline, polycrystalline, or amorphous depending on the substrate and the deposition process. The layers can be grown directly on the silicon substrate or on a suitable intermediate layer covering the substrate, e.g. an oxide or nitride layer. Instead of a single layer also multiple layers can be grown on top of each other.
In many applications it is useful to have electrical connections between the front-side and the backside of the silicon wafer. Such connections can be made e.g. by first forming holes through the wafer, then forming an insulating layer on the walls of the holes, and finally filling the holes with an electrically conductive material of sufficiently low resistivity. A suitable material is e.g. a metal or doped polycrystalline silicon. Electrical through-wafer connections are now commonly used and are called through-wafer-vias (TWV). Through-wafer-vias can also be created by first forming holes only part way through the wafer, then forming an insulating layer on the surfaces of the hole, then filling the hole with conductive material, and finally thinning the wafer from the backside to expose the bottom end of the filled hole. To be useful for many device applications the through-wafer-vias should be of sufficiently small diameter e.g. less than 50 μm or even less than 20 μm. For the electrical resistance of the through-wafer connection to be sufficiently low, the material used for filling the hole must be of low electrical resistivity; typically less than 0.01 ohm-cm or even lower.
Chemical vapour deposition (CVD) is the most commonly used method for the deposition of silicon. The CVD process utilises a silicon-containing precursor, possibly mixed with either an inert or a reducing carrier gas, e.g. nitrogen (N2) or hydrogen (H2). Silicon hydrides (e.g. silane SiH4), silicon chlorides (e.g. silicon tetrachloride SiCl4), or chlorosilicon hydrides (e.g. dichlorosilane SiH2Cl2 or trichlorosilane SiHCl3) are used as silicon precursors. If the layers are thin, low temperature deposition processes below 1050° C. can be used. If the deposited layer is thick, however, e.g. over 10 μm, the deposition rate becomes important due to its effect on the throughput of the deposition equipment. At high temperatures, above about 1100° C., the CVD processes can achieve very high deposition rates of up to 5 μm/min depending on the gas flow rates, temperature, and pressure. In particular, thick epitaxial and polycrystalline silicon layers are usually deposited using a high temperature of between 1050° C. and 1200° C. and either silicon tetrachloride or trichlorosilane as the precursor. However, at low temperatures below 650° C. usually silane is the most common silicon precursor.
Polycrystalline silicon layers can be alloyed with impurity atoms to achieve suitable electrical properties of the resulting alloy. In particular, the conductivity of the layer can be adjusted with the dopants boron for p-type layers and arsenic, phosphorus, or antimony for n-type layers. Typical precursors for the dopants in the CVD process are hydrides, e.g. diborane (B2H2) for boron. SiH4 is commonly used as the silicon precursor. Typical electrically active dopant atom concentrations in the grown layers are between 1014 cm−3 and 1019 cm−3. Both higher and lower concentrations are possible and also fairly commonly used. In principle low resistivity silicon can be used for through-wafer-vias, however there are some serious practical difficulties.
To achieve acceptable cost, high throughput and deposition rate are needed. Deposition rate can be increased using higher deposition temperature; but at temperatures above 620° C. the deposition process becomes too efficient with nearly 100% of the injected silane precursor being used growing silicon either on the wafers or the hot inner surfaces of the reactor. This inevitably tends to cause very poor uniformities of the grown layers as local deposition rates are limited by the availability of the precursor. In addition, with increasing temperature it becomes more difficult to deposit p-type silicon with low electrical resistivity, severely limiting the usefulness of such material for through-wafer-vias. For these reasons, the chemical vapour deposition of low resistivity p-type polycrystalline silicon layers is done at relatively low temperatures, typically at or below 620° C. If very low resistivity is required, the deposition is done below 600° C., and the grown layer is mostly amorphous. For the deposition of silicon at such low temperatures, using silane as a precursor for silicon and diborane (B2H6) for boron, a carrier gas is generally not used. The deposition rate of silicon is greatly reduced from that possible at high temperatures, typical values being around 5 nm/min or even less. To achieve reasonable throughput batch processing is used, with typically several tens or even hundreds of wafers being processed simultaneously in the same furnace. In such cases it becomes difficult to achieve uniform layers, with the layer thickness and resistivity exhibiting great variations, typically several tens of percent, between different wafers, and even within a single wafer. Therefore, it is not possible to find a good combination of high throughput, low cost, acceptable uniformity, and low resistivity with the typical SiH4/B2H6 process for many through-wafer-via applications.
To remove the problems of low uniformity and high resistivity of the low temperature SiH4/B2H6 low-pressure CVD (LPCVD) process boron trichloride has been used as the boron precursor. Noda et al. describe in U.S. Pat. No. 6,905,963 B2 an LPCVD method of growing below 600° C. boron doped polysilicon of greatly improved uniformity of layer thickness. However, according to Noda et al. above about 600° C. the specific resistance of the polycrystalline silicon increases sharply. In U.S. Pat. No. 7,419,701 B2 Herner et al. describe an LPCVD method of depositing boron doped polysilicon below 550° C. with SiH4 and boron trichloride (BCl3) to achieve very high B concentrations between 7*1020−3*1021. Furthermore, Herner et al. describe the use of this method to deposit in-situ doped polysilicon on a sidewall of a trench on the silicon wafer.
However, the low temperature processes described by Noda et al. and Herner et al. have the disadvantage of low deposition rate and low throughput and high cost for thick boron doped polysilicon layers.